數(shù)字電子技術(shù)試驗報告

武漢職業(yè)技術(shù)學(xué)院電信學(xué)院

數(shù)字電子技術(shù)實驗報告

實驗科目:數(shù)字電子技術(shù)實驗（五）

實驗名稱:譯碼顯示電路的應(yīng)用

實驗專業(yè):光電子技術(shù)光電09305

實驗者：朱軍

實驗時間:201*年11月8日

實驗指導(dǎo)教師:黃老師

武漢職業(yè)技術(shù)學(xué)院

實驗（訓(xùn)）項目單(Trainingitem)編制部門：電子資訊工程學(xué)院編制人：朱軍日期：201*.11.08

項目編號課程名稱訓(xùn)練目的五項目名稱譯碼顯示電路的應(yīng)用教材訓(xùn)練對象電信工程學(xué)院電子類學(xué)生學(xué)時3數(shù)字電子技術(shù)實驗數(shù)字電子技術(shù)、電子技能實訓(xùn)1)掌握中規(guī)模集成電路的功能。2)學(xué)習(xí)共陰極七段顯示器的使用方法。3)學(xué)會中規(guī)模集成數(shù)字電路的分析方法、設(shè)計方法和測試方法。1．實訓(xùn)設(shè)備和器件數(shù)字電路實驗箱、共陰極七段顯示器、74LS48芯片一片、74LS04芯片兩片、導(dǎo)線若干74LS4874LS04數(shù)字電路實驗箱七段數(shù)碼顯示器七段數(shù)碼顯示器74LS4874SL042．實訓(xùn)電路圖

3．內(nèi)容及實訓(xùn)步驟：（1）測74LS48的功能測74LS48的功能，直接將七個共陰極的發(fā)光二極管與74LS48的輸出端連接，然后再一一檢測。①器件檢測。用萬用表歐姆檔測量連接導(dǎo)線的好壞，然后將這些導(dǎo)線將發(fā)光二極管與電源+5V連接，檢測發(fā)光二極管的好壞。②74LS48檢測。a.將集成塊輸出端與發(fā)光二極管連接起來，同時用鉛筆做上記號，標(biāo)注a-g的字母。然后再將輸入端與開關(guān)（共地）連接起來，Vcc、GND分別接電源+5V和地。b.讓試燈輸入端，滅燈輸入端分別接低電平和高電平，如果所有的發(fā)光二極管都亮，說明集成塊是好的。c.再測試集成塊其它的功能，功能表如下：功能或數(shù)字滅燈試燈動態(tài)滅零0123456789輸入LT×011111111111RBI××01×××××××××A3××00000000001A2××00001111000A1××00010011001A0××00100001000BI/RBI0（輸入）101111111111輸出a0101011011110b0101111101110c0101101111110d0101011010111e0101010000101f0101000110110g0100011110111顯示字形滅燈滅燈（2）組成一個將二進(jìn)制（BCD碼）譯成以十進(jìn)制數(shù)方式顯示的電路由于74LS48正常工作時輸出的是高電平，而本數(shù)字實驗箱上的七段顯示器是共陽極的，所以要將輸出電平反向后才輸入到顯示器中。74LS04中含有六個反向器，因此此試驗要用兩片。a.在應(yīng)用74LS04之前，還是需要逐個的對每個反向器進(jìn)行檢測，以判斷所有的反向器是不是都是好的。方法是在一個反向器輸入端接開關(guān)，輸出端接發(fā)光二極管，同時Vcc和GND分別接+5V和地，然后將開關(guān)波動，輸入高電平時，二極管不亮；輸入低電平時，二極管亮。b.在檢測74LS48的功能的基礎(chǔ)上，按照電路圖將74LS48和74LS04、七段共陽極顯示器連接起來。然后改變各輸入端的狀態(tài)，觀察顯示器的變化，記錄的結(jié)果如上。4．實訓(xùn)總結(jié)與分析⑴由實驗可知，若當(dāng)BI/RBO做輸入端時,且BI=0時，無論輸入狀體如何，顯示都為零。⑵當(dāng)試燈輸入LT=0時，，BI/RBO是輸出端，且RBO=1，此時所有顯示段都發(fā)亮，顯示字形“8”。所以該輸入端可用于檢查74LS48本身及顯示器的好壞。⑶當(dāng)RBI=0、LT=1、輸入代碼A3A2A1A0=0000時，數(shù)碼段無任何顯示。

擴(kuò)展閱讀：數(shù)字電子技術(shù)實驗報告

數(shù)字電子技術(shù)實驗報告

院系：電氣工程學(xué)院專業(yè)：電氣工程及自動化年級：201*班號：0802姓名：學(xué)號：

0

","p":{"h":14.971,"w":3.05,"x":135.187,"y":1174.078,"z":1},"ps":{"_enter":1},"t":"word","r":[11]}],"page":{"ph":1263.375,"pw":893.25,"iw":0,"ih":0,"v":6,"t":"4","pptlike":false,"cx":135.187,"cy":114.937,"cw":629.354,"ch":1074.112}})目錄

實驗一組合邏輯電路分析....................................................................2

一、實驗?zāi)康?.........................................................................2二、預(yù)習(xí)內(nèi)容..........................................................................2三、實驗元件..........................................................................2四、實驗內(nèi)容..........................................................................3五、實驗數(shù)據(jù)及結(jié)果....................................................................4六、實驗總結(jié)..........................................................................4實驗二組合邏輯實驗（一）................................................................5半加器和全加器.............................................................................5

一、實驗?zāi)康?.........................................................................5二、預(yù)習(xí)內(nèi)容..........................................................................5三、實驗元件..........................................................................5四、實驗內(nèi)容..........................................................................7五、實驗數(shù)據(jù)及結(jié)果....................................................................8六、實驗總結(jié)..........................................................................9實驗三組合邏輯實驗（二）................................................................10數(shù)據(jù)選擇器和譯碼器的使用..................................................................10

一、實驗?zāi)康?........................................................................10二、預(yù)習(xí)內(nèi)容.........................................................................10三、實驗元件.........................................................................10四、實驗內(nèi)容.........................................................................12五、實驗數(shù)據(jù)及結(jié)果...................................................................14六、實驗總結(jié).........................................................................15實驗四觸發(fā)器和計數(shù)器.....................................................................16

一、實驗?zāi)康?........................................................................16二、預(yù)習(xí)內(nèi)容.........................................................................16三、實驗元件.........................................................................16三、實驗內(nèi)容及結(jié)果...................................................................19四、實驗總結(jié).........................................................................22實驗五555集成定時器.....................................................................23

一、實驗?zāi)康?........................................................................23二、預(yù)習(xí)內(nèi)容.........................................................................23三、實驗元件.........................................................................23四、實驗內(nèi)容及效果","p":{"h":13.5,"w":6.75,"x":288.375,"y":911.728,"z":174},"ps":null,"t":"word","r":[6]},{"c":"...................................................................28五、實驗總結(jié).........................................................................31實驗六數(shù)字秒表...........................................................................32

一、實驗?zāi)康?........................................................................32二、預(yù)習(xí)內(nèi)容.........................................................................32三、實驗元件.........................................................................32四、設(shè)計內(nèi)容及要求...................................................................32五、原理框架圖.......................................................................32六、實驗電路圖以及簡單分析...........................................................33七、實驗體會.........................................................................33

1

實驗一組合邏輯電路分析

一、實驗?zāi)康?/p>

1、了解熟悉各個邏輯元件的使用。2、熟悉了解組合邏輯電路的分析。

二、預(yù)習(xí)內(nèi)容

1、復(fù)習(xí)組合邏輯電路的分析的原理和方法。2、復(fù)習(xí)各種邏輯元件的使用。

三、實驗元件

1、四2輸入與非門74LS00

其結(jié)構(gòu)及引腳如圖所示：

","p":{"h":18.458,"w":6.772,"x":710.775,"y":593.062,"z":51},"ps":null,"t":"word","r":[13]},{"c":"。其中14號引腳接+5V高電平，7號引腳接地。其邏輯關(guān)系表達(dá)式為Y=AB

2、雙4輸入與非門74LS20

其結(jié)構(gòu)及引腳如圖所示：

其中14號引腳接+5V高電平，7號引腳接地。其邏輯關(guān)系表達(dá)式為Y=ABCD

2

1、分析下圖組合邏輯電路并將數(shù)據(jù)記錄下來。

VCC5VJ1X11U1A5Key=174LS00DJ22VCC02.5VU1C7Key=274LS00DJ33U1B6Key=3J4474LS00DKey=4

2、密碼鎖

密碼鎖的開鎖條件是：撥對密碼，鑰匙插入鎖眼將電源接通，當(dāng)兩個條件同時滿足時，開鎖信號為“1”，將鎖打開。否則，報警信號為“1”，接通警報，分析密碼ABCD是什么。

VCC5VVCC5VJ131112","p":{"h":5.894,"w":6.8,"x":723.237,"y":832.329,"z":579},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[27]},{"c":"密碼鎖電路圖為：

X12.5VX22.5VKey=1J21VCC0VCCU2B74LS00DU1A4U2C74LS00D10U3A7U1C8U1DKey=2974LS00D52J3U1B74LS20D74LS00D74LS00DU2A74LS00D74LS00D6Key=3J4Key=4

3

1、組合邏輯電路真值表

A0000000011111111B0000111100001111C0011001100110011D0101010101010101Y0001000100011111=AB+CD由真值表得出邏輯關(guān)系表達(dá)式為Y=ABCD

2、密碼鎖的真值表如下

A0000000011111111B0000111100001111C0011001100110011D0101010101010101X1000","p":{"h":16.966,"w":7.774,"x":602.79,"y":685.128,"z":441},"ps":{"_cover":true,"_scaleX":0.916},"t":"word","r":[10]},{"c":"0000001000000X21111111110111111即由真值表可得密碼鎖的密碼為ABCD=1001

六、實驗總結(jié)

1、通過實驗重新了解認(rèn)識了組合邏輯電路分析的步驟，由邏輯電路推導(dǎo)出組合邏輯電路的真值表和邏輯表達(dá)式的方法

2、通過這次實驗更加了解了了元件74LSS00和74LS20的內(nèi)部結(jié)構(gòu)和引腳的使用。

4

組合邏輯實驗（一）

半加器和全加器

一、實驗?zāi)康?/p>

熟悉用門電路設(shè)計組合電路的原理和方法步驟

二、預(yù)習(xí)內(nèi)容

1、復(fù)習(xí)用門電路設(shè)計組合邏輯電路的原理和方法2、復(fù)習(xí)二進(jìn)制數(shù)的運算

3、利用下列元器件完成：

（1）完成“異或”門、“與非”門、“與或非”門設(shè)計全加器的邏輯圖。

（2）完成用“異或”門設(shè)計的3變量判奇電路的原理圖。

三、實驗元件

1、四位全加器74LS283

其邏輯及引腳圖如圖所示：

其中16接+5V高電平，8端口接地，端口12、14、3、5對應(yīng)的加數(shù)的A3A2A1A0","p":{"h":13.184,"w":6.232,"x":744.569,"y":1072.537,"z":83},"ps":null,"t":"word","r":[16]},{"c":"，端口11、15、2、6對應(yīng)的被加數(shù)B3B2B1B0，端口10、13、1、4對應(yīng)的相加的和S3S2S1S0，端口7對應(yīng)的為相加前的進(jìn)位C1，端口9對應(yīng)的相加后的進(jìn)位C3。

5

、","p":{"h":17.466,"w":4.378,"x":158.804,"y":111.465,"z":4},"ps":null,"t":"word","r":[5]},{"c":"與或非門74LS51

其邏輯及引腳圖如圖所示：

端口14接+5V高電平，端口7接高電平，其他端口對應(yīng)數(shù)據(jù)符號如圖所示，邏輯表達(dá)式如上圖。

3、異或門（OC門）74LS136

其邏輯及引腳圖如圖所示：

端口14接+5V高電平，端口7接地，其他端口輸入如圖所示，其邏輯表達(dá)式為Y=AB。

6

1、用與非門組成半加器

設(shè)計電路圖如圖所示：

VCC5VVCCX12.5VU1DJ1146X22.5V74LS00DU1AU2AKey=10U1C574LS00DJ274LS00D274LS00DKey=2U1B7374LS00D

如圖連接電路按照表格中的數(shù)據(jù)設(shè)置電路數(shù)據(jù)，測量結(jié)果記錄入表格中。

2、用異或門、與或非門、與非門組成全加器

設(shè)計電路圖如圖所示：

VCC5VJ1VCC5VVCCVCCVCC5VX1X22.5V2.5VKey=101","p":{"h":8.027,"w":4.558,"x":301.371,"y":779.732,"z":515},"ps":{"_cover":true,"_enter":1,"_scaleX":1.001},"t":"word","r":[33]},{"c":"R11.0kU1AU1B4R21.0kJ2274LS136DVCC74LS136D3Key=2J3571121391011U2A86U3AKey=374LS00D74LS51D

如圖連接電路按照表格中的數(shù)據(jù)設(shè)置電路數(shù)據(jù)，測量結(jié)果記錄入表格中。

7

、用異或門設(shè)計3變量判奇電路，要求變量中的1的個數(shù)為奇數(shù)時，輸出為1。否則輸出

為0。

設(shè)計電路如圖所示：

VCC5VJ1VCC5VVCCVCCVCC5VX1Key=101R11.0kU1AU1B4R21.0k2.5VJ23274LS136DVCC74LS136DKey=2J35Key=3

如圖連接電路按照表格中的數(shù)據(jù)設(shè)置電路，測量結(jié)果記錄入表格中。4、“74LS283”全加器邏輯功能能測試。","p":{"h":17.466,"w":3.559,"x":135.187,"y":720.6,"z":37},"ps":null,"t":"word","r":[1]},{"c":"

連接元件74LS283，如表格中所示設(shè)置全加器數(shù)據(jù)并測試結(jié)果記錄入表格。

五、實驗數(shù)據(jù)及結(jié)果

1、用與非門組成半加器

iBi+AiBi；Ci=AiBi邏輯表達(dá)式為：Si=A

與理論相符合。

8

、用異或門、與或非門、與非門組成全加器數(shù)據(jù)表格。

邏輯表達(dá)式為：Si=AiBiCi1；Ci=AiBi+(AiBi)Ci1與理論相符合。

3、用異或門設(shè)計3變量判奇電路。

輸入A輸入B輸入C輸出L

00000011010101101001101011","p":{"h":17.507,"w":7.829,"x":668.292,"y":460,"z":148},"ps":{"_cover":true,"_scaleX":0.894},"t":"word","r":[18]},{"c":"001111實驗數(shù)據(jù)與理論值相同。

4、“74LS283”全加器邏輯功能測試

測試結(jié)果與理論值相同。

六、實驗總結(jié)

1、通過自己設(shè)計運行全加器和設(shè)計3變量判奇電路更加了解全加器的內(nèi)部結(jié)構(gòu)和異或

門與或非門與或門的使用。

2、通過74LS283邏輯功能的驗證更加熟悉了解了全加器的使用。

9

組合邏輯實驗（二）數(shù)據(jù)選擇器和譯碼器的使用

一、實驗?zāi)康?/p>

熟悉數(shù)據(jù)選擇器和數(shù)據(jù)分配器的邏輯功能和掌握其使用方法。

二、預(yù)習(xí)內(nèi)容

1、了解所用元件的邏輯功能和管腳排列。2、復(fù)習(xí)有關(guān)數(shù)據(jù)選擇器和譯碼器的內(nèi)容。

+3、用八選一數(shù)據(jù)選擇器產(chǎn)生邏輯函數(shù)L=ABC+ABCABC","p":{"h":18.459,"w":8.867,"x":661.2,"y":487.237,"z":59},"ps":null,"t":"word","r":[13]},{"c":"+ABC和

L=ABC。

4、用3線-8線譯碼器和與非門構(gòu)成一個全加器。

三、實驗元件

1、數(shù)據(jù)選擇器74LS151

其管腳端口如圖所示：

10

當(dāng)使能端EN=0是，Y是A2、A1、A0和輸入數(shù)據(jù)D0~D7的與或函數(shù)，其表達(dá)式為：Y=7i=0miDi，式中mi是A2、A1、A0構(gòu)成的最小項，顯然當(dāng)Di=1時，其對應(yīng)的最小項mi在于或表達(dá)式中出現(xiàn)。當(dāng)Di=0時，對應(yīng)的最小項就不出現(xiàn)。

2、3-8線譯碼器74LS138其管腳端口如圖所示：

74HC138管腳圖:74LS138為3線－8線譯碼器，共有54/74S138和54/74LS138兩

種線路結(jié)構(gòu)型式，其工作原理如下：

當(dāng)一個選通端（G1）為高電平，另兩個選通端（/(G2A)和/(G2B)）為低電平時，可將地址端（A、B、C）的二進(jìn)制編碼在一個對應(yīng)的輸出端以低電平譯出。

利用","p":{"h":15.75,"w":31.537,"x":193.77,"y":1000.995,"z":107},"ps":null,"t":"word","r":[2]},{"c":"G1、/(G2A)和/(G2B)可級聯(lián)擴(kuò)展成24線譯碼器；若外接一個反相器還可級聯(lián)擴(kuò)展成32線譯碼器。

若將選通端中的一個作為數(shù)據(jù)輸入端時，74LS138還可作數(shù)據(jù)分配器。3線-8線譯碼器74LS138的功能表如下圖：

11

四、實驗內(nèi)容

1、數(shù)據(jù)選擇器的使用

將數(shù)據(jù)選擇器的地址信號A2、A1、A0作為函數(shù)的輸入變量，數(shù)據(jù)輸入D0~D7作為控制信

號，控制各最小項在輸出邏輯函數(shù)中是否出現(xiàn)，使能端EN始終保持低電平，這樣，八選一數(shù)據(jù)選擇器就成為一個三變量的函數(shù)產(chǎn)生器。

（1）用八選一數(shù)據(jù)選擇器74LS151產(chǎn)生邏輯函數(shù)

將表達(dá)式寫為：L=m1D1+m3D3+m6D6+m7D7

該式符合標(biāo)準(zhǔn)表達(dá)式，顯然令D1、D3、D5、D7都應(yīng)該等于1，而式中沒有出現(xiàn)的最小項m0、m2、m4、m5，他們的控制信號D0、D2、D4、D5都應(yīng)該等于0。由此可畫出該邏輯函數(shù)產(chǎn)生器的邏輯圖。

L=A","p":{"h":18.458,"w":9.812,"x":331.155,"y":924.112,"z":111},"ps":null,"t":"word","r":[9]},{"c":"BC+ABC+ABC+ABC

12

5VVCC5VX12.5VU1J143D0542D1Y1D26Key=1VCCGND15D3~W14D413D5GND12D6D7J2121110A9BC7~GKey=2374LS151DVCCJ3GNDKey=3GND2）用八選一數(shù)據(jù)選擇器74LS151產(chǎn)生邏輯函數(shù)

根據(jù)上述74LS151的工作原理自行設(shè)計邏輯圖完成邏輯函數(shù)L=ABC

VCCVCCX15V5V2.5VVCCU1J143D0Y542D11D215D3~W6Key=1GND14D413D512D6GNDD7J2","p":{"h":13.835,"w":13.085,"x":295.124,"y":889.836,"z":350},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[36]},{"c":"121110A9BC7~GKey=2374LS151DVCCJ3GNDKey=3GND13

（

、3-8線譯碼器的應(yīng)用

用3-8線譯碼器74LS138和與非門構(gòu)成一個全加器。寫出邏輯表達(dá)式并設(shè)計電路圖驗證試驗結(jié)果。

VCC5VVCC5V2.5V2.5VX1X2J1VCC11U114U2A12Key=1GND2123645ABCG1~G2A~G2BJ23Y0Y1Y2Y3Y4Y5Y6Y715141312111097569871074LS20DU2BKey=2VCCGND74LS138D74LS20DJ3GNDKey=3GND

五、實驗數(shù)據(jù)及結(jié)果

1、數(shù)據(jù)選擇器的使用

（1）用八選一數(shù)據(jù)選擇器74LS151產(chǎn)生邏輯函數(shù)L=ABC+ABC+ABC+ABC真值表如下圖：

輸入A輸入B輸入C輸出L

00000011010001111000101011011111即可得函數(shù)表達(dá)式為：L=","p":{"h":15.75,"w":11.765,"x":305.25,"y":1088.82,"z":228},"ps":null,"t":"word","r":[28]},{"c":"ABC+ABC+ABC+ABC

14

2）用八選一數(shù)據(jù)選擇器74LS151產(chǎn)生邏輯函數(shù)L=ABC

真值表如下圖

輸入A輸入B輸入C輸出L

00000011010101101001101011001111即可得函數(shù)表達(dá)式為：L=ABC

2、3-8線譯碼器的應(yīng)用

真值表如圖所示：

輸入A輸入B輸入C輸出L1輸出L201*0000110010100110110010101011100111111即可得其邏輯表達(dá)式為：L1=ABC；L2=AB+(AB)C符合全加器邏輯關(guān)系，完成實驗。

六、實驗總結(jié)","p":{"h":23.662,"w":5.205,"x":280.47,"y":794.878,"z":348},"ps":{"_enter":1},"s":{"font-family":"e4e587976bec0975f465e2af0080010"},"t":"word","r":[19]},{"c":"1、通過該實驗對于數(shù)據(jù)選擇器74LS151和數(shù)據(jù)譯碼器74LS138的功能有了更清楚的認(rèn)識了解。

2、通過自己根據(jù)邏輯關(guān)系設(shè)計電路熟悉和掌握電路的設(shè)計。

15

觸發(fā)器和計數(shù)器

一、實驗?zāi)康?/p>

1、熟悉J-K觸發(fā)器的基本邏輯功能和原理。2、了解二進(jìn)制計數(shù)器的工作原理。

3、設(shè)計并驗證十進(jìn)制、六進(jìn)制計數(shù)器。

二、預(yù)習(xí)內(nèi)容

1、復(fù)習(xí)有關(guān)R-S觸發(fā)器、J-K觸發(fā)器、D觸發(fā)器的內(nèi)容。

2、預(yù)習(xí)有關(guān)計數(shù)器的工作原理。

3、用74LS163和與非門組成四位二進(jìn)制計數(shù)器，十進(jìn)制計數(shù)器，六十進(jìn)制計數(shù)器。設(shè)計電路圖。

三、實驗元件

1、四2輸入與非門74LS00其結(jié)構(gòu)及引腳如圖所示：

。其中14號引腳接+5V高電平，7號引腳接地。其邏輯關(guān)系表達(dá)式為Y=AB

此實驗中將管腳12與13或者10","p":{"h":17.466,"w":16.984,"x":375.12,"y":1024.65,"z":82},"ps":null,"s":{"letter-spacing":"1.013"},"t":"word","r":[8]},{"c":"與9或者1與2或者4與5連接起來將與非門當(dāng)做反

相器來使用。

16

、可預(yù)置四位二進(jìn)制計數(shù)器74LS163（同步清零）

74LS163的管腳圖如下圖所示：

74LS163的真值表如下圖所示：

PTCP功能1111↑計數(shù)φφ01↑并行輸入0111φ保持1011φ保持(RC=0)0φφ","p":{"h":16.189,"w":8.438,"x":372.87,"y":707.599,"z":395},"ps":{"_cover":true},"t":"word","r":[17]},{"c":"0φ清零74LS163邏輯功能表74LS163的時序圖如下圖所示：

17

、七段譯碼驅(qū)動器74LS248

七段譯碼驅(qū)動器74LS248管腳圖如下圖所示：","p":{"h":15.75,"w":3.559,"x":480.975,"y":135.12,"z":8},"ps":{"_enter":1},"t":"word","r":[1]},{"c":"

七段譯碼驅(qū)動器74LS248功能表如下圖所示：

18

1、六進(jìn)制計數(shù)器

根據(jù)74LS163以及74LS00的邏輯功能設(shè)計出電路圖如下圖所示。

U2DCD_HEXVCC5V3456710VCC14321U1GNDABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211155432912U3A74LS00D6V120Hz5VGND74LS163DGND試驗成功。","p":{"h":17.466,"w":3.559,"x":135.187,"y":927.795,"z":24},"ps":null,"t":"word","r":[4]},{"c":"

GND

電腦仿真以及實驗接線如上圖，觀察數(shù)字等顯示為0~5的范圍，及滿足六進(jìn)制計數(shù)器規(guī)則，

19

、十進(jìn)制計數(shù)器

根據(jù)74LS163以及74LS00的邏輯功能設(shè)計出電路圖如下圖所示。

U2DCD_HEXVCC5V3456710VCC14321U1GNDABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211155432912U3A74LS00D6V120Hz5VGND74LS163DGND

GND

電腦仿真以及實驗接線如上圖，觀察顯示數(shù)字范圍為0~9，即滿足十進(jìn)制顯示規(guī)則，實驗成","p":{"h":15.75,"w":234.391,"x":524.925,"y":766.8,"z":19},"ps":null,"s":{"letter-spacing":"-0.132"},"t":"word","r":[5]},{"c":"功。

20

、六十進(jìn)制計數(shù)器

根據(jù)74LS163、74LS248以及74LS00的邏輯功能設(shè)計出電路圖如下圖所示。

U2U5VCC5V3456710911DCD_HEXU1ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211154657DCD_HEX432143212U3A74LS00D32V120Hz5VGND74LS163DGND11GNDVCCU43456710912ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211158974LS163D10","p":{"h":8.485,"w":9.763,"x":352.896,"y":720.265,"z":464},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[23]},{"c":"U6A74LS00DGND

電腦仿真如上圖，數(shù)字顯示范圍為0~59，滿足六十進(jìn)制規(guī)則，試驗成功。

21

GNDVCC5VVCC5V3456710911GNDCKGNDU4CKU5ABCDEFGABCDEFGU1ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO141312111510467VCCU67126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG131211109151419202122232425VCCU3A74LS00D274LS248DV11Hz5V74LS163D121314151617182U2GNDU7QAQBQCQDRCO141312111538953456710912ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG1312111091514U3B74LS00D74LS248D74LS163D11GND

操作實驗接線如上圖，觀察數(shù)字顯示范圍為0~59，滿足六十進(jìn)制規(guī)則，試驗成功。

四、實驗總結(jié)

1、通過該實驗更加熟悉了解了可預(yù)置四位二進(jìn)制計數(shù)器74LS163的功能和使用。

2、通過該實驗熟悉掌握了用可預(yù)置四位二進(jìn)制計數(shù)器74LS163","p":{"h":17.466,"w":52.983,"x":504.629,"y":829.845,"z":20},"ps":null,"t":"word","r":[30]},{"c":"設(shè)計完成各種進(jìn)制的計數(shù)器。

22

555集成定時器

一、實驗?zāi)康?/p>

熟悉與使用555集成定時器

二、預(yù)習(xí)內(nèi)容

復(fù)習(xí)有關(guān)555集成定時器的內(nèi)容和常用電路。

三、實驗元件

555集成定時器：

555時基電路是一種將模擬功能與邏輯功能巧妙地結(jié)合在同一硅片上的組合集成電路。該電路可以在最基本的典型應(yīng)用方式的基礎(chǔ)上，根據(jù)實際需要，經(jīng)過參數(shù)配置和電路的重新組合，與外接少量的阻容元件就能構(gòu)成不同的電路，因而555電路在波形的產(chǎn)生與變換、測量與控制、家用電器、電子玩具等許多領(lǐng)域中都得到了廣泛應(yīng)用。","p":{"h":15.75,"w":3.559,"x":592.5,"y":627.15,"z":41},"ps":null,"t":"word","r":[9]},{"c":"

（一）555集成定時器的內(nèi)部結(jié)構(gòu)和邏輯功能

1.內(nèi)部結(jié)構(gòu)及邏輯功能

23

圖1為555時基電路的電路結(jié)構(gòu)和8腳雙列直插式的引腳圖，由圖可知555電路由電阻分壓器、電壓比較器、基本RS觸發(fā)器、放電管和輸出緩沖器5個部分組成。它的各個引腳功能如下：

1腳：GND(或Vss)外接電源負(fù)端VSS或接地，一般情況下接地。

8腳：VCC(或VDD)外接電源VCC，雙極型時基電路VCC的范圍是4.5～16V，CMOS型時基電路VCC的范圍為3～18V。一般用5V。

3腳：OUT（或Vo）輸出端。2腳：TR低觸發(fā)端。6腳：TH高觸發(fā)端。

4腳：R是直接清零端。當(dāng)R端接低電平，則時基電路不工作，此時不論TR、TH處于何電平，時基電路輸出為“0”，該端不用時應(yīng)接高電平。

5腳：CO(或VC)為控制電壓端。若此端外接電壓，則可改變內(nèi)部兩個比較器的基準(zhǔn)電壓，當(dāng)該端不用時，應(yīng)將該端串入一只0.01μF電容接地，以防引入干擾。

7腳：D放電端。該端與放電管集電極相連，用做定時器時電容的放電。電阻分壓器由三個5kΩ的等值電阻串聯(lián)而成。電阻分壓器為比較器C1、C2提供參考電壓，比較器C1的參考電壓為2/3Vcc，加在同相輸入端，比較器C2的參考電壓為1/3Vcc，加在反相輸入端。比較器由兩個結(jié)構(gòu)相同的集成運放C1、C2組成。高電平觸發(fā)信號加在C1的反相輸入端，與同相輸入端的參考電壓比較后，其結(jié)果作為基本RS觸發(fā)器R端的輸入信號；低電平觸發(fā)信號加在C2的同相輸入端，與反相輸入端的參考電壓比較后，其結(jié)果作為基本RS觸發(fā)器S端的輸入信號。基本RS觸發(fā)器的輸出狀態(tài)受比較器C1、C2的輸出端控制。

在1腳接地，5腳未外接電壓，兩個比較器C1、C2基準(zhǔn)電壓分別為2/3Vcc，1/3Vcc的情況下，555時基電路的功能表如表1示。","p":{"h":15.75,"w":3.559,"x":431.4,"y":837.72,"z":162},"ps":{"_enter":1},"t":"word","r":[1]},{"c":{"ix":0,"iy":0,"iw":893,"ih":230},"p":{"h":230,"opacity":1,"w":893.249,"x":0,"y":110,"z":163},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_25_163.png"},"t":"pic"},{"c":{"ix":0,"iy":235,"iw":893,"ih":274},"p":{"h":274,"opacity":1,"w":893.249,"x":0,"y":860.25,"z":164},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_25_164.png"},"t":"pic"},{"c":"

24

時基電路的主要參數(shù)

555時基電路的主要參數(shù)有電源電壓、靜態(tài)電流、定時精度、閾值電壓、閾值電流、觸發(fā)電壓、觸發(fā)電流、復(fù)位電壓、復(fù)位電流、放電電流、驅(qū)動電流及最高工作頻率。

（二）555集成定時器的應(yīng)用1．單穩(wěn)態(tài)電路

前面介紹的雙穩(wěn)態(tài)觸發(fā)器具有兩個穩(wěn)態(tài)的輸出狀態(tài)

和

，兩個狀態(tài)始終相反。而單

穩(wěn)態(tài)觸發(fā)器只有一個穩(wěn)態(tài)狀態(tài)。在未加觸發(fā)信號之前，觸發(fā)器處于穩(wěn)定狀態(tài)，經(jīng)觸發(fā)后，觸發(fā)器由穩(wěn)定狀態(tài)翻轉(zhuǎn)為暫穩(wěn)狀態(tài)，暫穩(wěn)狀態(tài)保持一段時間后，又會自動翻轉(zhuǎn)回原來的穩(wěn)定狀態(tài)。單穩(wěn)態(tài)觸發(fā)器一般用于延時和脈沖整形電路。

單穩(wěn)態(tài)觸發(fā)器電路的構(gòu)成形式很多。圖下圖所示為用555定時器構(gòu)成的單穩(wěn)態(tài)觸發(fā)器，R、C為外接元件，觸發(fā)脈沖u1由2端輸入。5端不用時一般通過0.01uF電容接地，以防干擾。下面對照圖進(jìn)行分析。","p":{"h":15.75,"w":189.412,"x":135.187,"y":978.495,"z":57},"ps":null,"t":"word","r":[4]},{"c":{"ix":0,"iy":0,"iw":893,"ih":478},"p":{"h":478,"opacity":1,"w":893.25,"x":0,"y":231,"z":58},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_58.png"},"t":"pic"},{"c":{"ix":0,"iy":483,"iw":893,"ih":22},"p":{"h":22,"opacity":1,"w":893.249,"x":0,"y":821,"z":59},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_59.png"},"t":"pic"},{"c":{"ix":0,"iy":510,"iw":893,"ih":25},"p":{"h":25,"opacity":1,"w":893.249,"x":0,"y":818,"z":60},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_60.png"},"t":"pic"},{"c":"

25

(1)穩(wěn)態(tài)

接通電源后，

經(jīng)R給電容C充電，當(dāng)uc上升到大于

時，基本RS觸發(fā)器復(fù)位，，若不加觸發(fā)信號，即

輸出u0=0。同時，晶體管T導(dǎo)通，使電容C放電。此后uc，則u0保持0狀態(tài)。電路將一直處于這一穩(wěn)定狀態(tài)。

(2)暫穩(wěn)態(tài)

在t=t1瞬間，2端輸入一個負(fù)脈沖，即u1觸發(fā)器保持原狀態(tài)，u0仍為高電平。在t=t3時刻，當(dāng)uc上升略高于

時，

=0，

=1，基本RS觸發(fā)器復(fù)位，輸出

)，若ucord","r":[0]}],"page":{"ph":1263.375,"pw":893.25,"iw":893,"ih":997,"v":6,"t":"4","pptlike":false,"cx":0,"cy":108,"cw":893.25,"ch":1081.049}})2．多諧振蕩器

多諧振蕩器又稱為無穩(wěn)態(tài)觸發(fā)器，它沒有穩(wěn)定的輸出狀態(tài)，只有兩個暫穩(wěn)態(tài)。在電路處于某一暫穩(wěn)態(tài)后，經(jīng)過一段時間可以自行觸發(fā)翻轉(zhuǎn)到另一暫穩(wěn)態(tài)。兩個暫穩(wěn)態(tài)自行相互轉(zhuǎn)換而輸出一系列矩形波。多諧振蕩器可用作方波發(fā)生器。

如下圖所示是由555定時器構(gòu)成的多諧振蕩器。R1、R2和C是外接元件。

剛接通電源時，uc=0，u0=1。當(dāng)uc升至

后，比較器C1輸出低電平(

=0)，基本

RS觸發(fā)器置0，定時器輸出u0由1變?yōu)?。同時，三極管T導(dǎo)通，電容通過R2放電，uc下降。在輸出低電平(

"style","c":[0],"s":{"bold":"true","font-size":"23.662"}},{"t":"style","c":[0,2,3,4,5,6,7,8,9,15,16,17,22,23,24,1],"s":{"color":"#000000"}},{"t":"style","c":[6,8,2],"s":{"font-family":"e4e587976bec0975f465e2af005001d"}},{"t":"style","c":[4,6,7,8,23,3],"s":{"font-size":"15.75"}},{"t":"style","c":[7,4],"s":{"font-family":"e4e587976bec0975f465e2af001001d"}},{"t":"style","c":[4,7,24,5],"s":{"font-family":"e4e587976bec0975f465e2af001001d"}},{"t":"style","c":[8,6],"s":{"font-size":"15.75"}},{"t":"style","c":[7],"s":{"letter-spacing":"-0.11"}},{"t":"style","c":[8],"s":{"letter-spacing":"0.037"}},{"t":"style","c":[9],"s":{"color":"#000000"}},{"t":"style","c":[9,11,14,18,20,21,10],"s":{"font-family":"e4e587976bec0975f465e2af00b001d","font-size":"12.409"}},{"t":"style","c":[21,11],"s":{"letter-spacing":"-0.16"}},{"t":"style","c":[13,17,12],"s":{"font-family":"e4e587976bec0975f465e2af00c001d"}},{"t":"style","c":[13],"s":{"color":"#ff0000","font-size":"9.012"}},{"t":"style","c":[20,14],"s":{"letter-spacing":"-1.096"}},{"t":"style","c":[16,17,15],"s":{"font-size":"10.135"}},{"t":"style","c":[16],"s":{"font-family":"e4e587976bec0975f465e2af013001d","letter-spacing":"-0.465"}},{"t":"style","c":[17],"s":{"font-family":"e4e587976bec0975f465e2af00c001d","letter-spacing":"-0.495"}},{"t":"style","c":[20,21,18],"s":{"color":"#0000ff"}},{"t":"style","c":[18,20,21,19],"s":{"color":"#0000ff"}},{"t":"style","c":[20],"s":{"color":"#0000ff"}},{"t":"style","c":[21],"s":{"color":"#0000ff"}},{"t":"style","c":[23,22],"s":{"font-family":"e4e587976bec0975f465e2af009001d"}},{"t":"style","c":[23],"s":{"font-family":"e4e587976bec0975f465e2af009001d"}},{"t":"style","c":[24],"s":{"font-size":"13.5"}}],"body":[{"c":"四、實驗內(nèi)容及效果

1、555單穩(wěn)電路根據(jù)555集成定時器的內(nèi)部結(jié)構(gòu)和原理設(shè)計555單穩(wěn)電路如下圖所示：

R2=100KΩ時，

VCC5VVCCX1U1555_TIMER_RATEDVCCRSTDISTHROUT42.5VR1100k213TRICONGNDV11kHz5VC110uF-POL0C210nF理論上tw=RCln3=1.1RC≈1.1s

仿真實驗時，在運行時間t=1.1時，等熄滅一下。運用示波器觀察當(dāng)時時刻波形顯示如圖所示：

實際操作實驗時，指示燈也在約為1秒左右時熄滅一瞬間，即實驗與理論值基本相同，試驗成功。

28

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VCC5VU1555_TIMER_RATEDR11.0MRST1VCCX12.5VVCCOUT4DISTHR23TRICONGNDV11kHz5VC110uF-POL0C210nF

理論上tw=RCln3=1.1RC≈11s

仿真實驗時，在運行時間t=11時，等熄滅一下。運用示波器觀察當(dāng)時時刻波形顯示如圖所示：

實際操作實驗時，指示燈也在約為11秒左右時熄滅一瞬間，即實驗與理論值基本相同，試驗成功。

29

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根據(jù)555集成定時器的內(nèi)部結(jié)構(gòu)和原理設(shè)計555多諧振蕩器電路如下圖所示：

VCC5VVCCGXSC1U1555_TIMER_RATEDABCDTR1100k1VCCRSTOUT4R210k23DISTHRTRICONGNDC1270pFC210nF0示波器仿真結(jié)果如下圖：

根據(jù)連讀元件參數(shù)計算理論值為：

f=

tpL

11.43

=+tpHR1+2R2C其中tpL=0.7R2C，tpH=0.7（R1+R2）C，根據(jù)示波器顯示以及比例符合理論值，試驗成功。

30

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根據(jù)555集成定時器的內(nèi)部結(jié)構(gòu)和原理設(shè)計接近開關(guān)電路如下圖所示：接近開關(guān)要求觸摸一下接觸線，LED亮一秒鐘。

VCC5VU1555_TIMER_RATEDVCCR1100kRSTDIS1VCCOUT2THRTRI3C3100nFCONGNDC14.7uF-POLC210nF0LED1

從2號端口接出一根導(dǎo)線，將另一端口放向遠(yuǎn)處，當(dāng)有任何物體接近導(dǎo)線端口或者移動改變導(dǎo)線端口燈亮，及與理論效果相同，試驗成功。

五、實驗總結(jié)

1、通過該實驗不僅讓我們從理論上更從實踐上熟悉了解了555集成定時器的內(nèi)部結(jié)構(gòu)以及

邏輯功能。2、通過這次實驗熟悉掌握了555集成定時器的各種用法以及功能。

31

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一、實驗?zāi)康?/p>

1、了解數(shù)字計時裝置的及泵年工作原理和簡單設(shè)計方法。

2、熟悉中規(guī)模集成器件和半導(dǎo)體顯示器的使用。

3、了解簡單數(shù)字裝置的調(diào)試方法，驗證所涉及的數(shù)字秒表的功能。

二、預(yù)習(xí)內(nèi)容

1、N進(jìn)制計數(shù)器、譯碼顯示電路以及多謝振蕩器的工作原理和設(shè)計方法。2、所用期間的功能和外部引線排列。

三、實驗元件

555集成定時器、四2輸入與非門74LS00、可預(yù)置四位二進(jìn)制計數(shù)器74LS163、雙4輸入與非門74LS20、七段譯碼驅(qū)動器74LS248以及相關(guān)元件。

四、設(shè)計內(nèi)容及要求

1、設(shè)計一個數(shù)字秒表電路，電路包含秒脈沖發(fā)生器、計數(shù)、譯碼。顯示范圍為：00~592、數(shù)字秒表電路應(yīng)具有清零、停止、啟動的功能。

五、原理框架圖

譯碼電路譯碼電路數(shù)碼顯示器譯碼電路秒計數(shù)器32

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GNDGNDGNDVCC5VGNDCKGNDCKU4J1Key=2J2Key=1U13451659U5ABCDEFGABCDEFGU6QAQBQCQDRCO14131211154849VCCGNDR1100k63U9555_TIMER_RATEDVCCRSTDIS6462ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBO710912OAOBOCODOEOFOG131211109151440414243444546U3COUT60U3A74LS00D74LS248DR2100k74LS00DTHRTRICONGND74LS163D53475033343536373839C2C14.7uF10nFU3B74LS00D61U257U7QAQBQCQDRCO1413121115515554523456710912ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG1312111091514U8A74LS20D5674LS248D74LS163D

電路中555集成定時器以及相關(guān)電阻電容構(gòu)成的為秒信號發(fā)生器，其頻率根據(jù)實驗五中555集成定時器構(gòu)成的多諧振蕩器計算得到。

兩個可預(yù)置四位二進(jìn)制計數(shù)器74LS163構(gòu)成秒計數(shù)器電路，兩個七段譯碼驅(qū)動器74LS248以及電燈構(gòu)成數(shù)碼顯示器電路，其中下方的七段譯碼驅(qū)動器74LS248可以不用，可以直接接四接口電燈。

電路中其他元件（開關(guān)以及四2輸入與非門74LS00、雙4輸入與非門74LS20）構(gòu)成控制電路。

其中開關(guān)1起清零作用，開關(guān)2起暫停作用。

七、實驗體會

這是本學(xué)期最后一次實驗，也是考試實驗，該實驗考察了本學(xué)期學(xué)習(xí)的各個元件特別是計數(shù)器的實驗是本學(xué)期實驗的一大重點，同時自行設(shè)計電路也讓我們學(xué)會將所學(xué)知識結(jié)合運用，合理協(xié)調(diào)配合得到我們想要方案。操作實驗中我們進(jìn)行的并不是非常順利，主要因為之前沒有進(jìn)行充分的復(fù)習(xí)準(zhǔn)備，同時操作時應(yīng)注意各個接口的接觸，以及七段譯碼驅(qū)動器74LS248運行需接上拉電阻等細(xì)節(jié)問題。

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